This invention relates to capacitor formation in semiconductor wafer processing, and to resultant capacitor constructions. The invention secondarily relates to conductive line formation in semiconductor wafer processing, and to resultant conductive line constructions.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area.
The principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. This invention concerns stacked capacitor cell constructions, including what are commonly known as crown or cylindrical container stacked capacitors. Aspects of the invention are also applicable to conductive line fabrication and resultant construction.